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product overview address spaces addressing modes control registers interrupt structure instruction set
S3C8444 product overview 1 ? 1 1 product overview sam8 product family samsung's new sam8 family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. a dual address/data bus architecture and a large number of bit- or nibble-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included to support real-time operations. many sam8 microcontrollers have an external interface that provides access to external memory and other peripheral devices. the sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum six cpu clocks) can be assigned to specific interrupt levels. S3C8444 microcontroller the S3C8444 single-chip microcontroller is fabricated using a highly advanced cmos process. its design is based on the powerful sam8 cpu core. stop and idle power-down modes were implemented to reduce power consumption. the size of the internal register file is logically expanded, increasing the addressable on-chip register space to 1040 bytes. a flexible yet sophisticated external interface is used to access up to 64-kbyt es of program and data memory. the S3C8444 is a versatile microcontroller that is ideal for use in a wide range of general-purpose applications such as cd-rom/dvd-rom drives. using the sam8 modular design approach, the following peripherals were integrated with the sam8 cpu core:
product overview S3C8444 1? 2 ? six configurable 8-bit general i/o ports ? one 8-bit n-channel, open-drain output port ? one 8-bit input port for a/d converter input or digital input ? full-duplex serial data port with one synchronous and three asynchronous (uart) operating modes ? two 8-bit timers with interval timer or pwm mode ? two 16-bit timer/counters with four programmable operating modes ? two programmable 8-bit pwm modules with corresponding output pins ? one 8-bit capture module with cap i nput pin ? a/d converter with 8 selectable input pins the S3C8444 is a versatile microcontroller that is ideal for use in a wide range of general-purpose rom-less applications such as cd-rom/dvd-rom drivers. figure 1?1. S3C8444 microcontroller
S3C8444 product overview 1 ? 3 features cpu ? sam8 cpu core memory ? 1040-byte of internal register file ? 4 - k byte internal program memory area external interface ? 64-kbyte external data memo ry area ? 64-kbyte external program memory (romless) ? 6 0 -kbyte external program memory (normal) instruction set ? 78 instructions ? idle and stop instructions instruction execution time ? 240 ns at 25 mhz f osc (minimum) interrupts ? 20 interrupt sources and 19 interrupt vectors ? seven interrupt levels ? fast interrupt processing (level0 and 3-7 only) timer/counters ? two 8-bit timers with interval timer or pwm mode (timers a and b) ? two 16-bit timer/counters with four programmable operating modes (timers c and d) general i/o ? six 8-bit general i/o ports (ports 0,1,2,3, 4, and 5) ? one 8-bit n-channel, open-drain output port (port 6) ? one 8-bit input port (for adc input or port 7 digital input) serial port ? full-duplex serial data port (uart) ? four programmable operating modes pwm and capture ? two output channels (pwm0, pwm1) ? 8-bit resolution with 2-bit prescaler ? 97.66-khz frequency (25 -mhz cpu clock) ? capture module with cap input pin analog-to-digital converter ? eight analog input pins ? 8- bit conversion resolution ? 7.68 -s conversion speed ( 25 -mhz cpu clock) operating temperature range ? ? 20 c to + 85 c operating voltage range ? 4.5 v to 5.5 v package type ? 80-pin qfp, 80 ?pin tqfp
product overview S3C8444 1? 4 block diagram port 0 port 3 port i/o & interrupt control sam8 cpu p0.0?p0.7 (a8?a15) reset port2 port 4 port 1 port 2 p2.0?p2.5 (control signal) p1.0?p1.7 (ad0?ad7) ea port 5 p5.0?p5.3 timers a and b serial port rxd txd port 6 p6.0?p6.7 timers c and d p2.6 p2.7 p5.4?p5.7 sam8 bus p4.0?p4.7 a/d converter adc0 /p7.0 ? adc7 /p7.7 av ss av ref pwm module pwm0 pwm1 sam8 bus capture (p3.6) ta tb tcck tdck tcg tdg v dd1 v dd2 ,v ss1 ,v ss2 external address/data bus 1040-byte register file p3.0?p3.7 figure 1?2. S3C8444 block diagram
S3C8444 product overview 1 ? 5 pin assignments p0.1 / a9 p0.0 / a8 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 v dd2 (ext. ) p2.7 / tb p2.6 / ta p2.5 / pm p2.4 / mr p2.3 / dm p2.2 / mw p2.1 / ds p2.0 / as rxd txd pwm1 pwm0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 reset nc as v ss1 (int.) x out x in p6.0 p6.1 p6.2 p6.3 p6.4 p6.5 p6.6 p6.7 p7.7 / adc7 p7.6 / adc6 p7.5 / adc5 p7.4 / adc4 p7.3 / adc3 av ss p7.2 / adc2 p7.1 / adc1 av ref p7.0 / adc0 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ea p1.7 / ad7 p1.6 / ad6 p1.5 / ad5 p1.4 / ad4 p1.3 / ad3 p1.2 / ad2 p1.1 / ad1 p1.0 / ad0 v dd1 (int.) p0.7 / a15 p0.6 / a14 p0.5 / a13 p0.4 / a12 p0.3 / a11 p0.2 / a10 p4.7 / int11 p4.6 / int10 p4.5 / int9 p4.4 / int8 p4.3 / int7 p4.2 / int6 p4.1 / int5 p4.0 / int4 v ss2 (ext.) p3.7 / wait p3.6 / cap p3.5 p3.4 p3.3 / tdg / int3 p3.2 / tcg / int2 p3.1 / tdck / int1 S3C8444 80-qfp (top view) p3.0 / tcck / int0 figure 1?3. S3C8444 pin assignments
product overview S3C8444 1? 6 pin assignments (c ontinued ) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S3C8444 80-tqfp (top view) 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 p7.0 / adc0 p4.7 / int11 p4.6 / int10 p4.5 / int9 p4.4 / int8 p4.3 / int7 p4.2 / int6 p4.1 / int5 p4.0 / int4 v ss2 (ext.) p3.7 / wait p3.6 / cap p3.5 p3.4 p3.3 / tdg / int3 p3.2 / tcg / int2 p3.1 / tdck / int1 p3.0 / tcck / int0 pwm0 pwm1 as nc reset ea p1.7 / ad7 p1.6 / ad6 p1.5 / ad5 p1.4 / ad4 p1.3 / ad3 p1.2 / ad2 p1.1 / ad1 p1.0 / ad0 v dd1 (int.) p0.7 / a15 p0.6 / a14 p0.5 / a13 p0.4 / a12 p0.3 / a11 p0.2 / a10 p0.1 / a9 p0.0 / a8 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 v dd2 (ext. ) p2.7 / tb p2.6 / ta p2.5 / pm p2.4 / mr p2.3 / dm p2.2 / mw p2.1 / ds p2.0 / as rxd txd vss1 (int.) x out x in p6.0 p6.1 p6.2 p6.3 p6.4 p6.5 p6.6 p6.7 p7.7 / adc7 p7.6 / adc6 p7.5 / adc5 p7.4 / adc4 p7.3 / adc3 av ss p7.2 / adc2 p7.1 / adc1 av ref figure 1?4. S3C8444 pin assignments
S3C8444 product overview 1 ? 7 pin descriptions table 1?1. S3C8444 pin descriptions pin name pin type pin description circuit type qfp pin number share pins p0.0 - p0.7 i/ o nibble programmable port; input or output mode selected by software; schmitt trigger input or push- pull, open-drain output with software assignable pull-ups; alternately configurable as external interface address lines a8 - a15. 3 2, 1, 80 - 75 a8 - a15 p1.0 - p1.7 i/o same general characteristics as port 0; alternately configurable as external interface address/data lines ad0 - ad7. 3 73 - 66 ad0 - ad7 p2. 0 - p2.7 i/o general i/o port with schmitt trigger input or push- pull output. bit programmable ; p 2 .0 / address strobe ( as ) p 2 .1 / data strobe ( ds ) p 2 .2 / memory write ( mw ) p 2 .3 / data memory select ( dm ) p 2 . 4 / memory read ( mr ) p 2 . 5 / program memory select ( pm ) p2.6 / timer a output (ta) p2.7 / timer b output (tb) 5 19 - 12 as, ds, mw, dm, mr, pm , ta, tb p3.0 - p3.7 i/o general i/o port with bit programmable pins. schmitt trigger input or push-pull output with software assignable pull-ups. input or output mode is selectable by software. p3.0 - p3.3 are alternately used as inputs for external interrupts int0 - int3, respectively (with noise filters and interrupt control): p3.0 / timer c clock input (tcck) / int0 p3.1 / timer d clock input (tdck) / int1 p3.2 / timer c gate input (tcg) / int2 p3.3 / timer d gate input (tdg) / int3 p3.6 / capture data input (cap) p3.7 / wait for slow memory interface 4 24 - 31 (see pin description) p4.0 - p4.7 i/o general i/o port with bit programmable pins. schmitt trigger input or push-pull, open-drain output with software assignable pull-ups. input or output mode is selectable by software. p4.0 - p4.7 can alternately be used as inputs for external interrupts int4 - int11, respectively (with noise filters and interrupt control) 4 33 - 40 int4 - int11
product overview S3C8444 1? 8 table 1?1. S3C8444 pin descriptions (continued) pin name pin type pin description circuit type qfp pin number share pins p5.0?p5.7 i/o general i/o port with nibble programmable pins. schmitt trigger input or push-pull, open-drain output mode. mode and pull-ups are assigned by software. 3 10?3 ? p6.0?p6.7 o n- channel, open-drain output port; the pin circuits can withstand loads up to 9 volts. 8 58?51 ? adc0?adc7 i analog input pins for a/d converter module. alternatively used as general-purpose digital input port 7. 2 41, 43?44, 46?50 p7.0?p7.7 av ref , av ss ? a/d converter reference voltage and ground ? 42, 45 ? rxd i/o serial data rxd pin for receive inp ut and transmit output (mode 0) 6 20 ? txd o serial data txd pin for transmit output and shift clock input (mode 0) 7 21 ? pwm0, pwm1 o pulse width modulation output pins 7 23, 22 ? ta, tb o output pins for timer a and timer b 5 13, 12 p2.6, p2.7 int0?int11 i external interrupt input pins 4 24?27, 33?40 p3.0?p3.3, p4.0?p4.7 tcck, tdck i external clock input for timer c and timer d 4 24, 25 p3.0, p3.1 tcg, tdg i gate input pins for timer c and timer d 4 26, 27 p3.2, p3.3 cap i capture data input for pwm module 4 30 p3.6 wait i input pin for the slow memory timing signal from the external interface 4 31 p3.7 reset i system reset pin (pull-up resistor: 220 k w ) 1 64 ? ea i external access (ea) pin with two modes: 5 v input: normal rom-less operation with external interface (0 v is not allowed) 9 v? 10 v input: for f actory test mode ? 65 ? v dd1 , v ss1 ? power input pins for cpu operation (internal) ? 74, 61 ? v dd2 , v ss2 ? power input pins for port output (external) ? 11, 32 ? x in , x out ? main oscillator pins ? 59, 60 ? as o address strobe 7 62 ? nc ? no connection pins (connect to v ss ) ? 62, 63 ? note vdd1 must be connected to vdd2 in users application circuit, vss1 & vss2 also.
S3C8444 product overview 1 ? 9 pin circuits table 1?2. pin circuit assignments for the S3C8444 circuit number circuit type S3C8444 assignments 1 input reset pin 2 input a/d converter input pins, adc0?adc7 3 i/o port 0, 1, and 5 4 i/o ports 3 and 4, tcck, tdck, tcg, tdg, cap, wait , int0?int11 5 i/o port 2 ( as, ds, mw, dm, mr, pm , ta,tb) 6 i/o serial port rxd pin 7 output serial port txd pin, pwm0, pwm1 and as 8 output port 6 (n-chann el, open-drain output with high current capability)
product overview S3C8444 1? 10 input pull-up resistor (typical 230 k w ) v dd figure 1?5. pin circuit type 1 ( reset reset ) in v ref adc logic input buffer ? + figure 1?6. pin circuit type 2 (adc0?adc7)
S3C8444 product overview 1 ? 11 p u l l - u p r e s i s t o r ( t y p i c a l 46 k w ) d a t a v d d i n / o u t p u l l - u p e n a b l e i n p u t v s s o p e n - d r a i n o u t p u t d i s a b l e v d d figure 1? 7. pin circuit type 3 (ports 0,1, and 5)
product overview S3C8444 1? 12 i n / o u t v s s v d d o u t p u t d i s a b l e d a t a e x t e r n a l i n t e r r u p t i n p u t i n p u t n o i s e f i l t e r p u l l - u p r e s i s t o r ( t y p i c a l 4 6 k w ) v d d p u l l - u p e n a b l e figure 1?8. pin circuit type 4 (ports 3 and 4, tcck, tdck, tcg, tdg, cap, wait, wait, int0?int11)
S3C8444 product overview 1 ? 13 in / out input v ss output disable v dd data selection bits for ports or other functions other function open- drain figure 1?9. pin circuit type 5 ( port 2, as, ds, mw, dm, mr as, ds, mw, dm, mr , pm pm , ta and tb )
product overview S3C8444 1? 14 i n / o u t v s s v d d o u t p u t d i s a b l e d a t a v d d e d g e d e t e c t i o n n o i s e f i l t e r i n p u t r ( 4 6 k w ) a figure 1?10. pin circuit type 6 (serial rxd pin)
S3C8444 product overview 1 ? 15 output v ss data v dd figure 1?11. pin circuit type 7 ( as , serial txd pin, pwm0, pwm1) note : circuit type 8 can withstand up to 9-volt loads. output v ss data figure 1?12. pin circuit type 8 (port 6)
S3C8444 electrical data 16 ? 1 16 electrical data in this section, S3C8444 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? dc electrical characteristics ? ac ele ctrical characteristics ? input timing for external interrupts (ports 3 and 4) ? input timing for reset ? i/o capacitance ? data retention supply voltage in stop mode ? stop mode release timing initiated by reset ? a./d converter electrical characteristics ? serial port timing characteristics in mode 0 (10 mhz) ? serial clock waveform ? serial port timing in mode 0 (shift register mode) ? external memory timing characteristics (10 mhz) ? external memory read and write timing ? recommended a/d converter circ uit for highest absolute accuracy ? main oscillator frequency (f osc1 ) ? main oscillator clock stabilization time (t st1 ) ? clock timing measurement at x in ? suboscillator clock stabilization time (t st2 ) ? characteristic curves
electrical data S3C8444 16? 2 table 16?1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? 0.3 to + 7.0 v input voltage v i1 port 6 only (open-drain) ? 0.3 to + 10 v v i2 all ports except port 6 ? 0.3 to v dd + 0.3 output voltage v o ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active 30 ma total pin current for ports 0, 2, 3, 4, 6 100 total pin current for ports 1 and 5 200 operating temperature t a ? 20 to + 85 c storage temperature t stg ? 65 to + 150 c table 16?2. d.c. electrical characteristics (t a = ? 20 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit input high v ih1 all input pins except v ih2 0.8 v dd ? v dd v voltage v ih2 x in v dd ? 0.5 input low voltage v il1 all input pins except v il2 ? ? 0.2 v dd v v il2 x in 0.4 output high voltage v oh1 v dd = 4.5 v to 5.5 v i oh = ? 1 ma port 1 only v dd ? 1.0 ? ? v v oh2 v dd = 4.5 v to 5.5 v i oh = ? 200 a all output pins except port 1 v dd ? 1.0
S3C8444 electrical data 16 ? 3 table 16?2. d.c. electrical characteristics (continued) (t a = ? 20 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 2 ma all output pins except port 5 ? ? 0.4 v v ol2 v dd = 4.5 v to 5.5 v i ol = 1.5 ma port 5 input high leakage current i lih1 v in = v dd all input pins except x in ? ? 3 a i lih2 v in = v dd x in 20 input low leakage current i lil1 v in = 0 v all input pins except x in , and reset ? ? ? 3 a i lil2 v in = 0 v x in ? 20 output high leakage current i loh1 v out = v dd all output pins except for port 6 ? ? 5 a i loh2 port 6 (open-drain) v out = 9 v 20 output low leakage current i lol v out = 0 v ? ? ? 5 a pull-up resistor r l1 v in = 0 v; v dd = 5 v 10% ports 0, 1, 4, 5, and rxd 30 4 6 80 k w r l2 v in = 0 v; v dd = 5 v 10% reset only 120 23 0 320 supply current (1) i dd1 v dd = 5 v 10% 25 mhz crystal oscillator ? 35 50 ma v dd = 5 v 10% 1 0 mhz crystal oscillator 30 i dd2 idle mode: v dd = 5 v 10% 25 mhz crystal oscillator 11 25 idle mode: v dd = 5 v 10% 10 mhz crystal oscillator 5 i dd3 stop mode; v dd = 5 v 10% 3 20 a note: supply current does not include current drawn through internal pull-up resistors or external output current loads.
electrical data S3C8444 16? 4 table 16?3. a.c. electrical characteristics (t a = ? 20 c to + 85 c, v dd = 4.5 v to 6.0v) parameter symbol conditions min typ max unit interrupt input high, low width t inth, t intl p3.0?p3.3, p4.0?p4.7 3 ? ? t cpu reset input low width t rsl input 22 ? ? t cpu notes : 1. the unit t cpu means one cpu clock period. 2. the oscillator frequency is the same as cpu clock frequency. t i n t l t i n t h 0 . 8 v d d 0 . 2 v d d figure 16?1. input timing for external interrupts (ports 3 and 4) t rsl 0.2 v dd reset figure 16?2. input timing for reset reset
S3C8444 electrical data 16 ? 5 table 16?4. input/output capacitance (t a = ? 20 c to + 85 c, v dd = 0 v ) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 16?5. data retention supply voltage in stop mode (t a = ? 20 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr 2 ? 6 v data retention supply current i dddr v dddr = 2 v ? ? 5 a v dd reset execution of stop instruction v dddr data retention mode stop mode reset occurs normal operating mode oscillation stabilization time t wait note : t wait is the same as 4096 x 32 x 1 / f osc . 0.2 v dd figure 16?3. stop mode release timing initiated by reset reset
electrical data S3C8444 16? 6 table 16?6. a/d converter electrical characteristics (t a = ? 20 c to + 85 c, v dd = 4.5 v to 6.0 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution 8 8 8 bit absolute accuracy (1) v dd = 5.12 v cpu clock = 18 mhz av ref = 5.12 v av ss = 0 v ? ? | 3 | lsb conversion time (2) t con t cpu 192 (3) ? ? s analog reference voltage av ref 2.56 ? v dd v analog ground av ss v ss ? ? v analog input voltage v ian av ss ? av ref v analog input impedance r an 2 ? ? m? notes : 1. excluding quantization error, absolute accuracy equals 1/2 lsb. 2. 'conversion time' is the time required from the moment a conversion operation starts until it ends. 3. t cpu is the cpu clock period. table 16?7. serial port timing characteristics in mode 0 (10 mhz) (t a = ? 20 c to + 85 c, v dd = 4.5 v to 6.0v, v ss = 0 v) parameter symbol min typ max unit serial port clock cycle time t sck 500 t cpu 6 700 ns output data setup to clock rising edge t s1 300 t cpu 5 ? clock rising edge to input data valid t s2 ? ? 300 output data hold after clock rising edge t h1 50 t cpu ? input data hold after clock rising edge t h2 0 ? ? serial port clock high, low width t high , t low 200 t cpu 3 400 notes : 1. all times are in ns and assume a 10 mhz input frequency. 2. the unit t cpu means one cpu clock period. 3. the oscillator frequency is identical to the cpu clock frequency.
S3C8444 electrical data 16 ? 7 t h i g h 0 . 8 v d d 0 . 2 v d d t l o w t s c k figure 16?4. serial clock waveform
electrical data S3C8444 16? 8 n o t e : t h e s y m b o l s s h o w n i n t h i s d i a g r a m a r e d e f i n e d a s f o l l o w s : t s c k s e r i a l p o r t c l o c k c y c l e t i m e t s 1 o u t p u t d a t a s e t u p t o c l o c k r i s i n g e d g e t s 2 c l o c k r i s i n g e d g e t o i n p u t d a t a v a l i d t h 1 o u t p u t d a t a h o l d a f t e r c l o c k r i s i n g e d g e t h 2 i n p u t d a t a h o l d a f t e r c l o c k r i s i n g e d g e d a t a o u t d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t s c k s h i f t c l o c k t s 1 t h 1 d a t a i n t s 2 t h 2 v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d figure 16?5. serial port timing in mode 0 (shift register mode)
S3C8444 electrical data 16 ? 9 table 16?8. external memory timing characteristics (10 mhz) (t a = ? 20 c to + 85 c, v dd = 4.5 v to 6.0 v) number symbol parameter normal timing extended timing min max min max 1 t da (as) address valid to as - delay 10 ? 50 ? 2 t das (a) as - to address float delay 35 ? 85 ? 3 t das (dr) as - to read data required valid ? 140 ? 335 4 t was as low width 35 ? 85 ? 5 t da (ds) address float to ds 0 ? 0 ? 6a t wds (read) ds (read) low width 125 ? 275 ? 6b t wds (write) ds (write) low width 65 ? 165 ? 7 t dds (dr) ds to read data required valid ? 80 ? 255 8 t hds (dr) read data to ds - hold time 0 ? 0 ? 9 t dds (a) ds - to address active delay 20 ? 70 ? 10 t dds (as) ds - to as delay 30 ? 80 ? 11 t ddo (ds) write data valid to ds (write) delay 10 ? 50 ? 12 t das (w) as - to wait delay ? 90 ? 335 13 t hds (w) ds - to wait hold time 0 ? 0 ? 14 t drw (as) r/ w valid to as - delay 20 ? 70 ? 15 t dds (dw) ds - to write data not valid delay 20 ? 70 ? notes : 1. all times are in ns and assume a 10 mhz input frequency. 2. wait state s add 100 ns to the time of numbers 3, 6a, 6b, and 7. 3. auto-wait states add 100 ns to the time of number 12.
electrical data S3C8444 16? 10 wait (p3.7) ds r/ w port a a8?a15, dm dm port ad d0?d7 a0?a7 as in out d0?d7 out wait window 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 figure 16?6. external memory read and write timing (see table 15?7 for a description of each timing point.)
S3C8444 electrical data 16 ? 11 v dd v dd note : the symbol 'r' signifies an offset resistor with a value of from 50 to 100 ohms. if this resistor is omitted, the absolute accuracy will be maximum of 4 lsbs. adc0?adc7 S3C8444 r analog input pin 10 f + ? 103 c 101 c reference voltage input av ss v ss av ref figure 16?7. recommended a/d converter circuit for highest absolute accuracy
electrical data S3C8444 16? 12 table 16?9. main oscillator frequency (f osc1 ) (t a = ? 20 c + 85 c, v dd = 4.5 v to 6.0 v) oscillator clock circuit test condition min typ max unit crystal c2 c1 x in x out c2 c1 x in x out cpu clock oscillation frequency 1 ? 18 mhz ceramic c2 c1 x in x out cpu clock oscillation frequency 1 ? 18 mhz external clock x in x out a a x in input frequency 1 ? 18 mhz table 16?10 . recommended oscillator constants (t a = ? 20 c + 85 c, v dd = 4.5 v to 6.0 v) manufacturer product name load cap (pf) oscillator voltage range (v) remarks c1 c2 min max tdk ccr20.0ms6 5 5 4.5 5.5 smd type ccr24.0m6 5 5 4.5 5.5 smd type ccr25.0m6 ? 5 4.5 5.5 smd type note : on-chip c: 30pf 20% built in.
S3C8444 electrical data 16 ? 13 table 16?1 1 . main oscillator clock stabilization time (t st1 ) (t a = ? 20 c + 85 c, v dd = 4.5 v to 6.0 v) oscillator test condition min typ max unit crystal v dd = 4.5 v to 6.0 v ? ? 20 ms ceramic stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 ms external clock x in input high and low level width (t xh , t xl ) 25 ? 500 ns note : oscillation stabilization time (t st1 ) is the time required for the cpu clock to return to its normal oscillation frequency after a power-on occurs, or when stop mode is ended by a reset signal. the reset should therefore be held at low level until the t st1 time has elapsed (see figure 15?3). x i n t x l t x h 1 / f o s c 1 v d d ? 0 . 5 v 0 . 4 v figure 16?8. clock timing measurement at x in
electrical data S3C8444 16? 14 characteristic curves note the characteristic values shown in the following graphs are based on actual test measurements. they do not, however, represent guaranteed operating values. i dd1 (ma) 4.5 v dd (v) (t a = 25 c) 5.0 5.5 f osc = 25 mhz f osc = 20 mhz 22 24 26 28 30 3 2 3 4 3 6 3 8 f osc = 10 mhz figure 16?9. idd1 vs vdd
S3C8444 electrical data 16 ? 15 i dd2 (ma) 4.5 v dd (v) (t a = 25 c) 5.0 5.5 f osc = 25 mhz f osc = 20 mhz 4 5 6 7 8 9 10 11 12 f osc = 10 mhz 13 figure 16?10. idd2 vs vdd i dd3 (na) 4.5 v dd (v) (t a = 25 c) 5.0 5.5 100 120 140 160 180 200 220 240 260 280 figure 16?11. idd3 vs vdd
electrical data S3C8444 16? 16 0 i ol (ma) 0. 2 v ol1 (v) 0 .4 (t a = 25 c) 0 .6 0 .8 1 .0 v dd = 4.5 v v dd = 5.5 v 1 .2 2 4 6 8 10 12 14 16 18 figure 16?12. iol vs vol1
S3C8444 electrical data 16 ? 17 0 i ol (ma) 0. 2 v ol2 (v) 0 .4 (t a = 25 c) 0 .6 0 .8 1 .0 v dd = 4.5 v v dd = 5.5 v 1 .2 2 4 6 8 10 12 14 16 18 figure 16?13. iol vs vol2
electrical data S3C8444 16? 18 0 i oh (ma) 2.4 v oh2 (v) 3.0 (t a = 25 c) 3.6 4.2 4.8 v dd = 4.5 v v dd = 5.5 v 5.4 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 figure 16?14. ioh vs voh2
S3C8444 mechanical data 17 ? 1 17 mechanical data note : dimensions are in millimeters. 17.90 0.3 14.00 0.2 (1.00) 80-qfp-1420c 23.90 0.3 #80 (0.80) #1 0.35 0.1 0.15 max 0.80 0.20 0.10 max 0.15 +0.10 - 0.05 0~8 2.65 0.10 3.00 max 0.05 min 0.80 0.20 20.00 0.2 0.80 figure 17?1. S3C8444 qfp standard package dimensions (in millimeters)
mechanical data S3C8444 17? 2 n o t e : d i m e n s i o n s a r e i n m i l l i m e t e r s . 1 4 . 0 0 b s c 1 2 . 0 0 b s c 8 0 - t q f p - 1 2 1 2 - a n 1 4 . 0 0 b s c 1 2 . 0 0 b s c # 8 0 ( 1 . 2 5 ) # 1 0 . 5 0 0 . 1 7 ~ 0 . 2 7 0 . 6 5 0 . 1 5 0 . 1 0 m a x 0 . 0 9 ~ 0 . 2 0 0 ~ 7 1 . 0 0 0 . 0 5 1 . 2 0 m a x 0 . 0 5 ~ 0 . 1 5 0 . 2 5 g a u g e p l a n e 0 . 0 8 m a x m figure 17?2. S3C8444 tqfp standard package dimensions (in millimeters)
S3C8444 development tools 18? 1 18 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. two types of debugging tools including hardware and software are provided: the in-circuit emulator, smds2, developed for s3c1 , s3c7 , s3c8 families of microcontrollers, and even more sophisticated and powerful in-circuit emulator, smds2+, for s3c7 , s3c8 families of microcontrollers. the smds2+ is a new and improved version of smds2. in the future smds2+ will replace smds2 and eventually smds2 will not be supported. samsung also offers support software that includes debugger, assembler, and a program for setting options. development tools versions as of the date of this publication, two versions of the smds are being supported: ? smds2 version 5.3 (s/w) and smds2 version 1.3 (h/w); last release: october, 1995. ? shine version 1.0 (s/w) and smds2+ version 1.0 (h/w); last release: january, 1997. smds v5.3 smds v5.3 is an assembly level debugger with user-friendly host interfacing that uses in-circuit emulator,smds2. shine samsung host interface for in-circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm88 the sasm88 is an relocatable assembler for samsung's s3c8 -series microcontrollers. the sasm88 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm88 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory.
development tools S3C8444 18? 2 hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value 'ff' is filled into the unused rom area upto the maximum rom size of the target device automatically. target boards target boards are available for all s3c8 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. ibm-pc at or compatible target application system internal bus main board personality board 5-volt power supply front panel board tb8444 target board eva chip rs-232c target cable pod figure 18?1. smds product configuration (smds2)
S3C8444 development tools 18? 3 bus smds2+ rs-232c pod target cable prom/mtp writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc at or compatible tb8444 target board eva chip target application system figure 18?2. smds product configuration (smds2+)
development tools S3C8444 18? 4 tb 8444 target board the tb 8444 target board is used for the S3C8444 microcontroller. it is supported by the smds2 or smds2+ development system. tb8444 sm1296a reset1 to user_v cc off on 40-pin connector 2 1 39 40 25 1 j101 144 qfp s3e8440 eva chip gnd v cc cn1 av ss p7.7 p7.6 p7.5 p7.4 p7.3 p7.2 p7.1 p7.0 av ref sw1 + stop + idle u3 u1 40-pin connector 2 1 39 40 j102 external triggers ch1 ch2 figure 18?3. tb 8444 target board configuration
S3C8444 development tools 18? 5 table 18?1. power selection settings for tb 8444 'to user_vcc' settings operating mode comments off on to user_vcc a target system smds2/smds2+ tb8444 v cc v ss v cc the smds2/smds2+ main board supplies v cc to the target board (evaluation chip) and the target system. off on to user_vcc a tb8444 target system smds2/smds2+ external v cc v ss v cc the smds2/smds2+ main board supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. note : the following symbol in the 'to user_vcc' setting colum n indicates the electrical short configuration: a table 18?2. using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2/smds2+ breakpoint and trace functions.
development tools S3C8444 18? 6 table 18?3. analog pin connection switch settings ( tb8444 ) analog pin switch operating mode dip sw1: on target board target system ? ? ? analog signals dip sw1: off target system ? ? ? holes drilled for direct connection ? ? ? adc0 | adc7 target board note : analog signals coming into the target board can easily introduce noise into the analog converter circuit. this can cause invalid conversion results. to reduce noise, you can use the analog pin switches to provide the shortest possible path for analog signals. to do this, turn all dip switches to the off position. then, connect the analog signal lines directly via the holes of the corresponding analog pins. idle led the green led is on when the evaluation chip( s3e8440 ) is in idle mode. stop led the red led is on when the evaluation chip( s3e8440 ) is in stop mode.
S3C8444 development tools 18? 7 40-pin connector j101 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 a9 p5.7 p5.5 p5.3 p5.1 vdd2 p2.6/ta dr dw as txd pwm0 p3.1/tdck/int1 p3.3/tdg/int3 p3.5 p3.7/ wait p4.0/int4 p4.2/int6 p4.4/int8 p4.6/int10 a8 p5.6 p5.4 p5.2 p5.0 p2.7/tb pm dm ds pxd pwm1 p3.0/tcck/int0 p3.2/tcg/int2 p3.4 p3.6/cap vss2 p4.1/int5 p4.3/int7 p4.5/int9 p4.7/int11 40-pin connector j102 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 p7.0/adc0 p7.1/adc1 av ss p7.4/adc4 p7.6/adc6 p6.7 p6.5 p6.3 p6.1 nc(x in ) v ss1 nc ea ad6 ad4 ad2 ad0 a15 a13 a11 av ref p7.2/adc2 p7.3/adc3 p7.5/adc5 p7.7/adc7 p6.6 p6.4 p6.2 p6.0 nc(x out ) nc reset ad7 ad5 ad3 ad1 v dd1 a14 a12 a10 figure 18?4. 40-pin connectors for tb 8444 ( S3C8444 , 80-qfp package)
development tools S3C8444 18? 8 40-pin connectors target board target system target cable for 80 qfp adapter part name: cs80qf order code: sm6501 1 2 39 40 41 42 79 80 80-qfp adapter order code: sm6402 j101 j102 note : two 40-pin flat cables can be used instead of the target cable and the 80-qfp adapter to connect the target board and the target system. figure 18?5. tb 8444 cable for 80-qfp adapter

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